From 4171d62d1b98f73ea54f7c489ba0db6065795a25 Mon Sep 17 00:00:00 2001 From: Imarok Date: Thu, 19 Dec 2019 16:52:47 +0000 Subject: [PATCH] Workaround for L3 cache detection of Ryzen 3000 This code is planned to get refactored or removed anyway, so just do a cheap workaround. Reviewed by: Imarok Fixes: #4360 Differential Revision: https://code.wildfiregames.com/D2353 This was SVN commit r23262. --- source/lib/sysdep/arch/x86_x64/cache.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/source/lib/sysdep/arch/x86_x64/cache.cpp b/source/lib/sysdep/arch/x86_x64/cache.cpp index 1be905aa04..761254c028 100644 --- a/source/lib/sysdep/arch/x86_x64/cache.cpp +++ b/source/lib/sysdep/arch/x86_x64/cache.cpp @@ -89,7 +89,8 @@ static x86_x64::Cache L1Cache(u32 reg, x86_x64::Cache::Type type) static const size_t associativityTable[16] = { 0, 1, 2, 0, 4, 0, 8, 0, - 16, 0, 32, 48, 64, 96, 128, x86_x64::Cache::fullyAssociative + // TODO: The second '16' does not obey to the specifications and is only a workaround. For a correct implementation please look here: https://community.amd.com/thread/244207 + 16, 16, 32, 48, 64, 96, 128, x86_x64::Cache::fullyAssociative }; static x86_x64::Cache L2Cache(u32 reg, x86_x64::Cache::Type type)